1. Field of the Invention
The present invention relates to emitter-coupled logic ("ECL") circuits and more specifically to controlling the output signals of such ECL circuits using CMOS compatible signals.
2. Art Background
FIG. 1 illustrates a typical ECL output buffer 10 without a current source control. As shown in FIG. 1, ECL output buffers are not normally turned off because of the difficulty in controlling the current source 11 that supplies the gate while maintaining DC and AC performance of the gate. While it is possible to shunt the power away from the differential stage (with another switch at the second level, for instance) of the ECL output 12, current is still flowing and contributes to chip power dissipation.
The conventional ECL output buffers as shown in FIG. 1 have their drawbacks and disadvantages. Products with application optional ECL outputs are burdened by the extra power supply currents that serve the unused outputs. The current of any particular application is typically never less than that of the application that uses the full complement of outputs. This current is small, but not negligible (often 3-10 mA per output or 15-50 mW) and will cause the application to run hotter than actually required. Therefore, it becomes desirable to be able to control the current source in ECL circuits.
An ECL gate, such as the one shown in FIG. 1, is often used in connection with signals in the CMOS logic levels. Translations between the logic levels of CMOS logic and the logic levels of CML ("current mode logic") or ECL logic are typically done using a differential amplifier with a "mid-swing" reference. FIG. 2 illustrates a typical ECL (CML) translator 20. Translator 20 can be an efficient translator if a mid-swing reference 21 is available, but for logic levels with non standard swings, or for mixed power supply voltage systems, this reference is often less than ideal.
The conventional translators as shown in FIG. 2 have their drawbacks and disadvantages. The voltage defined a "mid-swing" must be developed with either resistive or matched transistor voltage dividers. These circuits take up significant area and power that is not required for the intrinsic logic function being performed. Errors in the levels set by the reference voltage generators also contribute to variations in the propagation delay of the gate. Further, the conventional methods of translating between CMOS and CML levels use referenced generators which require some additional circuitry and power dissipation that is not used by the intrinsic logic function. Therefore, it is also desirable to be able to translate CMOS signals to levels compatible with CML cells.
Furthermore, in high performance digital logic, the high speed signals are typically ECL or CML, which must be routed and logically manipulated in bipolar circuitry. The lower speed logic may be CMOS for a reduction in power. The interface between these logic levels also requires a translator to convert the large swing CMOS levels to the small ECL/CML logic levels used in the high speed gates.
The addition of a level translator requires an increase in both speed and power, over what is required for the intrinsic logic function. In the typical CML multiplexer circuit 30 shown in FIG. 3, the high speed data channels would be connected to inputs A+and A-32 and B+and B-33 as the select input 34 is driven by a CMOS/CML translator 31. The translator 31 adds delay and power to the circuit 30 and performs no logic function in this configuration. Thus, it is further desirable to be able to multiplex CML compatible data signals using CMOS compatible signals to switch between channels without the added delay and power.
As will be described in the following, the present invention will disclose an ECL circuit with a power supply current control to allow the output to shut off to reduce system power supply load. The following description will also disclose an ECL circuit capable of translating CMOS signals to levels compatible with CML cells. Further, the following description will disclose an ECL circuit capable of multiplexing CML compatible data signal levels while using CMOS compatible signals to switch between channels.